DC Motor

entity dc is
Port ( clk : in STD_LOGIC;
psw : in STD_LOGIC_VECTOR (2 downto 0);
pdcm : out STD_LOGIC);
end dc;

architecture Behavioral of dc is
signal temp:std_logic_vector(7 downto 0);
signal sclkdiv:std_logic_vector(11 downto 0):="000000000000";
begin
process(clk)
begin
if (clk='1' and clk'event) then temp<=temp+'1';
end if;
end process;

process(temp(7))
begin
if (clk='1' and clk'event) then sclkdiv<=sclkdiv+1;
end if;
if (sclkdiv="101110111000") then sclkdiv<="000000000000";
end if;
end process;

process(psw,sclkdiv)
variable vdcm:bit;
begin
if (sclkdiv="000000000000") then vdcm:='1';
end if;
if (psw="000" and sclkdiv="000000000000") then vdcm:='0';
elsif (psw="001" and sclkdiv="000001111111") then vdcm:='0';
elsif (psw="010" and sclkdiv="000111010000") then vdcm:='0';
elsif (psw="011" and sclkdiv="100000000000") then vdcm:='0';
elsif (psw="100" and sclkdiv="111000000100") then vdcm:='0';
elsif (psw="101" and sclkdiv="111000000111") then vdcm:='0';
elsif (psw="110" and sclkdiv="111000000100") then vdcm:='0';
elsif (psw="111" and sclkdiv="111111111111") then vdcm:='0';
end if;
if (vdcm='1') then pdcm<='1';
else pdcm<='0';
end if;
end process;

end Behavioral;

Triangular

entity traingular is
Port ( clk,rst : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR (7 downto 0));
end traingular;

architecture Behavioral of traingular is
signal temp: std_logic_vector(7 downto 0);
signal counter: std_logic_vector(8 downto 0);
begin
process(clk,rst)
begin
if rst='1' then temp<=(others=>'0');
elsif (clk='1' and clk'event) then temp<=temp+'1';
end if;
end process;

process(temp(3),rst)
begin
if rst='1' then counter<="000000000";
elsif (temp(3)='0' and temp(3)'event) then counter<=counter+1;
end if;
end process;

process(counter)
begin
if counter(8)='1' then dout<=counter(7 downto 0);
else dout<= not(counter(7 downto 0));
end if;
end process;
end Behavioral;

Ramp

entity ramp is
Port ( clk,rst : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR (0 to 7));
end ramp;

architecture Behavioral of ramp is
signal temp: std_logic_vector(7 downto 0);
signal counter: std_logic_vector(7 downto 0);
begin
process(clk,rst)
begin
if rst='1' then temp<="00000000";
elsif (clk='1' and clk'event) then temp<=temp+1;
end if;
end process;

process(temp(2),rst)
begin
if rst='1' then counter<="00000000";
elsif (temp(2)='0' and temp(2)'event) then counter<=counter+1;
end if;
end process;

dout<=counter;
end Behavioral;

Stepper Motor

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity step is
Port ( clk,rst,dir : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR (3 downto 0));
end step;

architecture Behavioral of step is
signal int_clk: std_logic;
signal div_clk: std_logic_vector(30 downto 0);
signal shift_reg : std_logic_vector(3 downto 0);

begin
process(clk,rst)
begin

if rising_edge(clk) then div_clk<=div_clk+1;
end if;
end process;

int_clk<=div_clk(14);
process(rst,int_clk)
begin
if rst='1' then shift_reg<="0001";
elsif rising_edge(int_clk) then
if dir='1' then shift_reg<=shift_reg(2 downto 0) & shift_reg(3);
else shift_reg<=shift_reg(0) & shift_reg(3 downto 1);
end if;
end if;

end process;
dout<=shift_reg;
end Behavioral;

Relay

entity relays is
Port ( rst : in STD_LOGIC;
y : inout STD_LOGIC_VECTOR (1 downto 0));
end relays;

architecture Behavioral of relays is

begin
process(rst)
begin
if rst='1' then y<="00";
else y<="11";
end if;
end process;

end Behavioral;

Binary Up/down Counter

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity UP4 is
Port ( rst,clk : in STD_LOGIC;
cnt : out STD_LOGIC_vector(3 downto 0));
end UP4;

architecture Behavioral of UP4 is
signal temp: STD_LOGIC_vector(3 downto 0);
signal down_clk: STD_LOGIC_vector(30 downto 0);
signal int_clk: STD_LOGIC;
begin
process(clk,rst)
begin
if rst='1' then down_clk<=(others=>'0');
elsif(clk='1' and clk' event) then down_clk<= down_clk+1;
end if;
end process;
int_clk<= down_clk(21);
process(int_clk,rst)
begin
if rst='1' then temp<="0000"; --For Down counter temp<='1111'--
elsif int_clk='1' and int_clk' event then temp<=temp+1; -- for down counter temp<=temp-1--

end if;

end process;
cnt<= temp;
end Behavioral;

BCD Up Counter [VHDL]

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity BCDUP is
Port ( rst,clk : in STD_LOGIC;
cnt : out STD_LOGIC_vector(3 downto 0));
end BCDUP;

architecture Behavioral of BCDUP is
signal temp: STD_LOGIC_vector(3 downto 0);
signal down_clk: STD_LOGIC_vector(30 downto 0);
signal int_clk: STD_LOGIC;
begin
process(clk,rst)
begin
if rst='1' then down_clk<=(others=>'0');
elsif(clk='1' and clk' event) then down_clk<= down_clk+1;
end if;
end process;
int_clk<= down_clk(21);
process(int_clk,rst)
begin
if rst='1' then temp<="0000";
elsif int_clk='1' and int_clk' event then temp<=temp+1;
if temp="1001" then temp <= "0000";

end if;
end if;

end process;
cnt<= temp;

end Behavioral;

BCD Up Counter [VHDL]

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity BCDUP is
Port ( rst,clk : in STD_LOGIC;
cnt : out STD_LOGIC_vector(3 downto 0));
end BCDUP;

architecture Behavioral of BCDUP is
signal temp: STD_LOGIC_vector(3 downto 0);
signal down_clk: STD_LOGIC_vector(30 downto 0);
signal int_clk: STD_LOGIC;
begin
process(clk,rst)
begin
if rst='1' then down_clk<=(others=>'0');
elsif(clk='1' and clk' event) then down_clk<= down_clk+1;
end if;
end process;
int_clk<= down_clk(21);
process(int_clk,rst)
begin
if rst='1' then temp<="0000";
elsif int_clk='1' and int_clk' event then temp<=temp+1;
if temp="1001" then temp <= "0000";

end if;
end if;

end process;
cnt<= temp;

end Behavioral;

BCD Down Counter [VHDL]

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity counter2 is
Port ( count : out STD_LOGIC_VECTOR (3 downto 0);
rst,clk : in STD_LOGIC);
end counter2;

architecture Behavioral of counter2 is
signal temp : std_logic_vector( 3 downto 0);
signal down_clk : std_logic_vector(30 downto 0);
signal int_clk : std_logic;
begin

process (clk,rst)
begin
if rst ='1' then down_clk <= (others =>'0');
elsif (clk='1' and clk'event) then down_clk <= down_clk+1;
end if;
end process;
int_clk <= down_clk(21);
process ( int_clk,rst)
begin
if rst='1' then temp <= "1001";
elsif int_clk='1' and int_clk'event then temp <= temp-1 ;
if temp<="0000" then temp<="1001";
end if;
end if;
end process;
count <= temp;
end Behavioral;

Square Wave [VHDL Program]

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity SQR is
Port ( CLK,RST : in STD_LOGIC;
DAC_out : inout STD_LOGIC_VECTOR(0 TO 7));
end SQR;

architecture Behavioral of SQR is
SIGNAL TEMP: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL COUNTER: STD_LOGIC_VECTOR(7 DOWNTO 0);
begin
PROCESS (CLK,RST)
BEGIN
IF RST='1' THEN TEMP<="00000000";
ELSIF (CLK='1' AND CLK'event) THEN TEMP<= TEMP+'1';
END IF;
END PROCESS;
PROCESS(TEMP(2), RST)
BEGIN
IF RST='1' THEN COUNTER<="00000000";
ELSIF (TEMP(2)='0' AND TEMP(2)'EVENT) THEN COUNTER <= COUNTER+1;
END IF;
END PROCESS;
PROCESS (COUNTER)
BEGIN
IF COUNTER<=192 THEN DAC_out<="00000000";
ELSE DAC_out<="11111111";
END IF;
--127 FOR 50% DUTY CYCLE--
--64 FOR 75% DUTY CYCLE--
--192 FOR 25% DUTY CYCLE--
END PROCESS;


end Behavioral;