Ramp

entity ramp is
Port ( clk,rst : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR (0 to 7));
end ramp;

architecture Behavioral of ramp is
signal temp: std_logic_vector(7 downto 0);
signal counter: std_logic_vector(7 downto 0);
begin
process(clk,rst)
begin
if rst='1' then temp<="00000000";
elsif (clk='1' and clk'event) then temp<=temp+1;
end if;
end process;

process(temp(2),rst)
begin
if rst='1' then counter<="00000000";
elsif (temp(2)='0' and temp(2)'event) then counter<=counter+1;
end if;
end process;

dout<=counter;
end Behavioral;