Binary Up/down Counter

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity UP4 is
Port ( rst,clk : in STD_LOGIC;
cnt : out STD_LOGIC_vector(3 downto 0));
end UP4;

architecture Behavioral of UP4 is
signal temp: STD_LOGIC_vector(3 downto 0);
signal down_clk: STD_LOGIC_vector(30 downto 0);
signal int_clk: STD_LOGIC;
begin
process(clk,rst)
begin
if rst='1' then down_clk<=(others=>'0');
elsif(clk='1' and clk' event) then down_clk<= down_clk+1;
end if;
end process;
int_clk<= down_clk(21);
process(int_clk,rst)
begin
if rst='1' then temp<="0000"; --For Down counter temp<='1111'--
elsif int_clk='1' and int_clk' event then temp<=temp+1; -- for down counter temp<=temp-1--

end if;

end process;
cnt<= temp;
end Behavioral;