Stepper Motor

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity step is
Port ( clk,rst,dir : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR (3 downto 0));
end step;

architecture Behavioral of step is
signal int_clk: std_logic;
signal div_clk: std_logic_vector(30 downto 0);
signal shift_reg : std_logic_vector(3 downto 0);

begin
process(clk,rst)
begin

if rising_edge(clk) then div_clk<=div_clk+1;
end if;
end process;

int_clk<=div_clk(14);
process(rst,int_clk)
begin
if rst='1' then shift_reg<="0001";
elsif rising_edge(int_clk) then
if dir='1' then shift_reg<=shift_reg(2 downto 0) & shift_reg(3);
else shift_reg<=shift_reg(0) & shift_reg(3 downto 1);
end if;
end if;

end process;
dout<=shift_reg;
end Behavioral;