BCD Down Counter [VHDL]

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity counter2 is
Port ( count : out STD_LOGIC_VECTOR (3 downto 0);
rst,clk : in STD_LOGIC);
end counter2;

architecture Behavioral of counter2 is
signal temp : std_logic_vector( 3 downto 0);
signal down_clk : std_logic_vector(30 downto 0);
signal int_clk : std_logic;
begin

process (clk,rst)
begin
if rst ='1' then down_clk <= (others =>'0');
elsif (clk='1' and clk'event) then down_clk <= down_clk+1;
end if;
end process;
int_clk <= down_clk(21);
process ( int_clk,rst)
begin
if rst='1' then temp <= "1001";
elsif int_clk='1' and int_clk'event then temp <= temp-1 ;
if temp<="0000" then temp<="1001";
end if;
end if;
end process;
count <= temp;
end Behavioral;