DC Motor

entity dc is
Port ( clk : in STD_LOGIC;
psw : in STD_LOGIC_VECTOR (2 downto 0);
pdcm : out STD_LOGIC);
end dc;

architecture Behavioral of dc is
signal temp:std_logic_vector(7 downto 0);
signal sclkdiv:std_logic_vector(11 downto 0):="000000000000";
begin
process(clk)
begin
if (clk='1' and clk'event) then temp<=temp+'1';
end if;
end process;

process(temp(7))
begin
if (clk='1' and clk'event) then sclkdiv<=sclkdiv+1;
end if;
if (sclkdiv="101110111000") then sclkdiv<="000000000000";
end if;
end process;

process(psw,sclkdiv)
variable vdcm:bit;
begin
if (sclkdiv="000000000000") then vdcm:='1';
end if;
if (psw="000" and sclkdiv="000000000000") then vdcm:='0';
elsif (psw="001" and sclkdiv="000001111111") then vdcm:='0';
elsif (psw="010" and sclkdiv="000111010000") then vdcm:='0';
elsif (psw="011" and sclkdiv="100000000000") then vdcm:='0';
elsif (psw="100" and sclkdiv="111000000100") then vdcm:='0';
elsif (psw="101" and sclkdiv="111000000111") then vdcm:='0';
elsif (psw="110" and sclkdiv="111000000100") then vdcm:='0';
elsif (psw="111" and sclkdiv="111111111111") then vdcm:='0';
end if;
if (vdcm='1') then pdcm<='1';
else pdcm<='0';
end if;
end process;

end Behavioral;