Triangular

entity traingular is
Port ( clk,rst : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR (7 downto 0));
end traingular;

architecture Behavioral of traingular is
signal temp: std_logic_vector(7 downto 0);
signal counter: std_logic_vector(8 downto 0);
begin
process(clk,rst)
begin
if rst='1' then temp<=(others=>'0');
elsif (clk='1' and clk'event) then temp<=temp+'1';
end if;
end process;

process(temp(3),rst)
begin
if rst='1' then counter<="000000000";
elsif (temp(3)='0' and temp(3)'event) then counter<=counter+1;
end if;
end process;

process(counter)
begin
if counter(8)='1' then dout<=counter(7 downto 0);
else dout<= not(counter(7 downto 0));
end if;
end process;
end Behavioral;