Square Wave [VHDL Program]

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity SQR is
Port ( CLK,RST : in STD_LOGIC;
DAC_out : inout STD_LOGIC_VECTOR(0 TO 7));
end SQR;

architecture Behavioral of SQR is
SIGNAL TEMP: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL COUNTER: STD_LOGIC_VECTOR(7 DOWNTO 0);
begin
PROCESS (CLK,RST)
BEGIN
IF RST='1' THEN TEMP<="00000000";
ELSIF (CLK='1' AND CLK'event) THEN TEMP<= TEMP+'1';
END IF;
END PROCESS;
PROCESS(TEMP(2), RST)
BEGIN
IF RST='1' THEN COUNTER<="00000000";
ELSIF (TEMP(2)='0' AND TEMP(2)'EVENT) THEN COUNTER <= COUNTER+1;
END IF;
END PROCESS;
PROCESS (COUNTER)
BEGIN
IF COUNTER<=192 THEN DAC_out<="00000000";
ELSE DAC_out<="11111111";
END IF;
--127 FOR 50% DUTY CYCLE--
--64 FOR 75% DUTY CYCLE--
--192 FOR 25% DUTY CYCLE--
END PROCESS;


end Behavioral;